The inventive concept relates to a method of fabricating a vertical semiconductor device, and more particularly, to a method of fabricating a vertical semiconductor device including a single crystalline semiconductor layer.
Semiconductor devices may be variously employed for electronic and communication products. To increase the integration density of the semiconductor devices, a vast amount of research has been conducted on methods of stacking cell transistors included in a single chip in a vertical direction. In particular, since a single cell can include a single transistor in a NAND flash memory device, cell transistors may be vertically stacked so that the cell transistors can be more highly integrated. However, when cell transistors included in a semiconductor device are stacked in a vertical direction, it may be difficult to provide uniform operating characteristics for the cell transistors.
When active regions of the cell transistors are formed of a polysilicon layer, cell dispersion may be lower than when the active regions of the cell transistors are formed of a single crystalline semiconductor layer, and an on-current may be reduced which may decrease the operating speed of the semiconductor devices. Furthermore, when the active regions of the cell transistors are formed of the polysilicon layer, a tunnel oxide layer included in the cell transistors should be formed using a chemical vapor deposition (CVD) process.